Programmable logic evolution, FPGA vs. CPLD, FPGA essential building blocks, logic mapping to the FPGA, FPGA - Memory, Processor, DSP/Multiplier, serial I/Os, Clock management components, FPGA suppliers and differentiation

         Design Entry (including VHDL /Verilog, Schematic, State Diagram design entry methods), Normal Compilation, Functional simulation, Quick overview of ModelSim AE (Altera Edition)

         Verilog HDL Intro, Top down design model, Modules, Data types, Operators and Behavioral modeling.

          External Interface, Data flow modeling, Gate level modeling and Tasks and functions.

         VHDL Intro, Entities and Architectures, Instantiation and Port Maps, Structural modeling, Behavioral modeling

         Dataflow modeling, Synthesis of combinational logic and Synthesis of Sequential Logic.

         Mega Wizard Plug in Manager, I/O pin Assignment analysis, pin planner, pin assignments, board configuration settings, implementation in development board. Exercises: simple digital functions such (gates, F/F, encoder and decoder, mux and demux, counters etc...)

         Preparing a project for incremental flow, Creating design partitions, Combining with floor plan constraints using LogicLock, The TimeQuest Static Timing Analyzer, Concepts, Interface, Using TimeQuest from the GUI, Early timing estimation Optimization techniques Using PowerPlay power optimization, Early estimation, Using the power optimization adviser

         Debugging tool – signal Tap II Embedded Logic Analyzer, Take advantage of free Embedded Logic Analyzers to debug your design. The three modes, Configuration, Using the Logic Analysis Interface, Capturing/displaying, Saving data Advanced Triggering, Signal Probe and the logic analyzer interface, Purpose and use.

         Chip Planner, RTL Viewer, Technology Map Viewer, Design Flow Automation using TCL commands, Why and when to use DSP Builder Exercises, creating own design partitions, allocating FPGA logic elements, timing and power analysis for revision projects, signal taping for own codes.

         Why and when to use SoPC, available IPs, SoPC design flow, identifying standard and specific components, User interface, principles, step-by-step system generation, using the wizard and configuring the blocks, defining and customizing the NIOS II processor and tightly coupled memories.

         Main concepts, the NIOSII IDE, User interface, principles, step-by-step flow of creating a software project, Creating NiosII custom peripherals, basic tools for compilation and debugging, using signal Tap II Embedded Logic Analyzer for debugging.

         Sdram Controller, USB Controller, I2C Controller and Music Player

         System On Programmable Chip development for a real time application using Quartus, NIOS II and Altera IP core (a mini project, developed as a team).